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this x24012 device has been acquired by ic microsystems from xicor, inc. 1 start stop logic control logic slave address register +comparator h.v. generation timing & control word address counter xdec ydec d out ack e 2 prom 32 x 32 data register start cycle (8) v cc r/w pin (4) v ss (5) sda (6) scl (3) a 2 (2) a 1 (1) a 0 d out load inc ck 8 description the x24012 is a cmos 1024 bit serial e 2 prom, internally organized as one 128 x 8 bank. the x2401 2 features a serial interface and software protocol a llowing operation on a simple two wire bus. three address inputs allow up to eight devices to share a common two wire bus. xicor e 2 proms are designed and tested for applications requiring extended endurance. inherent data retenti on is greater than 100 years. the x24012 is avail able in eight pin dip and soic packages. features ? 2.7 to 5.5v power supply ? low power cmos ? active current less than 1 ma ?standby current less than 50 a ? internally organized 128 x 8 ? self timed write cycle ? typical write cycle time of 5 ms ? 2 wire serial interface ? bidirectional data transfer protocol ? four byte page write operation ? minimizes total write time per byte ? high reliability ? endurance: 10 0,000 cycles ?data retention: 100 years ? xicor, 1991 patents pending characteristics subject to change without notice 1k x24012 128 x 8 bit serial e 2 prom functional diagram 3847 fhd f01 3847-1 ic mic ic microsystems tm
x24012 2 pin configuration pin names symbol description a 0 ?a 2 address inputs sda serial data scl serial clock nc no connect v ss ground v cc +5v 3847 pgm t01 pin descriptions serial clock (scl) the scl input is used to clock all data into and ou t of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may b e wire -ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to th e guide- lines for calculating typical values of bus pull-up resistors graph. address (a 0 , a 1 , a 2 ) the address inputs are used to set the least signif icant three bits of the seven bit slave address. these in puts can be static or activ ely driven. if used statically they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven to v ss or to v cc . 3847 fhd f02 v cc nc scl sda a 0 a 1 a 2 v ss 1 2 3 4 8 7 6 5 x24012 dip/soic
x24012 3 device operation the x24012 supports a bidirectional bus oriented pr oto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving de vice as the receiver. the device controlling the transfer i s a master and the device being controlled is the slave . the master will always initiate data transfers and prov ide the clock for both transmit and receive operations. the re fore, the x24012 will be considered a slave in all applications . clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condi tion, which is a high to low transitio n of sda when scl is high. the x24012 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. figure 1. data validity figure 2. definition of start and stop scl sda data stable data change scl sda start bit stop bit 3847 fhd f05 3847 fhd f06
x24012 4 stop condition all communications must be terminated by a stop con di- tion, which is a low to high transition of sda when scl is high. the stop condition is also used by t he x24012 to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indica te successful data transfers. the transmitting device will release the bus after transmitting eight bits. duri ng the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of d ata. refer to figure 3. the x24012 will respond with an acknowledge after recognition of a start condition and its slave addr ess. if both the device and a write operation have been sel ected, the x24012 will respond with an acknowledge after the receipt of each subsequent eight bit word . in the read mode the x24012 will transmit eight bit s of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected an d no stop condition is generated by the master, the x24012 will continue to transmit data. if an acknowledg e is not detected, the x24012 will terminate further data tr ans- missions. the master must then issue a stop conditi on to return the x24012 to the standby power mode and place the device into a known state . figure 3. acknowledge response from receiver 3847 fhd f07 scl from master data output from transmitter 1 8 9 data output from receiver start acknowledge
x24012 5 bus master sda line bus activity: x24012 s t a r t slave address s s t o p p a c k a c k a c k a c k a c k word address n data n data n?1 data n+3 note: in this example n = xxxx 0000 (b); x = 1 or 0 sda line bus activity: x24012 s t a r t slave address s s t o p p a c k a c k a c k word address data device addressing following a start condition the master must output the address of the slave it is accessing. the most sign ificant four bits of the slave address are the devi ce type identifier (see figure 4). for the x24012 this is f ixed as 1010[b]. following the start condition, the x24012 monitors the sda bus comparing the slave address being transmit- ted with its slave address (device type and state o f a 0 , a 1 and a 2 inputs). upon a correct compare the x24012 outputs an acknowledge on the sda line. depending o n the state of the r/w bit, the x24012 will execute a rea d or write operation. write operations byte write for a write operation, the x24012 requires a second address field. this address field is the word addre ss, comprised of eight bits, providing access to any on e of the 128 words of memory. note: the most significant bit is a don?t care. upon receipt of the word address t he x24012 responds with an acknowledge, and awaits the next eight bits of data, again responding with an a c- knowledge. the master then terminates the transfer by generating a stop condition, at which tim e the x24012 begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the x 24012 inputs are disabled, and the device will not respon d to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. figure 4. slave address the next three significant bits address a pa rticular device. a system could have up to eight x24012 devices on the bus (see figure 10). the eight addresses are defined by the state of the a 0 , a 1 and a 2 inputs. the last bit of the slave address defines the opera tion to be performed. when set to one a read operation is selected, when set to zero a write operation is sel ected. figure 5. byte write figure 6. page write 1 0 1 0 a2 a1 a0 r/w device type identifier device address 3847 fhd f08 3847 fhd f09 3847 fhd f10 bus activity: master sda line bus activity: x24012 bus activity: master sda line bus activity: x24012
x24012 6 page write the x24012 is capable of an four byte page write operation. it is initiated in the same manner as th e byte write operation, but instead of terminating the wri te cycle after the first data word is transferred, the master can transmit up to three more words. after the receipt of each word, the x24012 will respond with an acknowledge. after the receipt of each word, the two low order a ddress bits are internally incremented by one. the high order five bits of the address remain constant. if the ma ster should transmit more than four words prior to generating the stop condition, the address counter will ?roll over? and the previously written data will be overwritten. as with the byte write operation, all inputs are disab led until completion of the internal write cycle. refer to fi gure 6 for the address, acknowledge and data transfe r sequence. acknowledge polling the disabling of the inputs, during the inte rnal write operation, can be used to take advantage of the typ ical 5 ms write cycle time. once the stop condition is i ssued to indicate the end of the host?s write operati on the x24012 initiates the internal write cycle. ack poll ing can be initiated immediately. this involves issuing the st art condition followed by the slave address for a write operation. if the x24012 is still busy with the write operation no ack will be returned. if the x24012 ha s completed the write operation an ack will be return ed and the master can then proceed with the next read or write operation (see flow 1). read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of t he slave address is set to a one. there are three basi c read operations: current address read, random read and sequential read. it should be noted that the ninth clock cycle of th e read operation is not a ?don?t care.? to terminat e a read operation, the master must either issue a stop cond ition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition . f low 1. ack polling sequence 3847 fhd f11 write operation completed enter ack polling issue start issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed issue stop no yes yes proceed issue stop no
x24012 7 bus activity: master sda line bus activity: x24012 s t a r t slave address s a c k s t a r t s word address n a c k slave address data n a c k s t o p p bus activity: master sda line bus activity: x24012 s t a r t slave address s s t o p p a c k data curr ent address read internally the x24012 contains an address counter t hat maintains the address of the last word acces sed, incremented by one. therefore, if the last access ( either a read or write) was to address n, the next read oper ation would ac cess data from address n + 1. upon receipt of the slave address with r/w set to one, the x240 12 issues an acknowledge and transmits the eight bit w ord during the next eight clock cycles. the read operat ion is terminated by the master; by not responding with an acknowledge and by issuing a stop condition. refer to figure 7 for the sequence of address, acknowledge a nd data transfer. random read random read operations allow the master to access a ny memory location in a random manner. prior to issuin g the slave address with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the start condition, and the slave ad dress followed by the word address it is to read. after the word address acknowledge, the master immediately reissue s the start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the x24012 and then by the eight bit word. the read operation is terminated by the master; by not respo nding w ith an acknowledge and by issuing a stop condition. refer to figure 8 for the address, acknowledge and data transfer sequence. figure 7. current address read 3847 fhd f12 figure 8. random read 3847 fhd f13
x24012 8 bus activity: master sda line bus activity: x24012 slave address a c k a c k data n+x s t o p p data n a c k data n+1 a c k data n+2 sequential read sequential read can be initiated as either a current address read or random access read. the first word is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional data. the x24012 continues to o ut- put data for each acknowledge received. the read operation is terminated by the master, by not respo nding with an acknowledge and by issuing a stop condition. the data output is sequential, with the data from a ddress n followed by the data from n + 1. the address counte r for read operations increments all address bits, al lowing the entire memory contents to be serially read during one operation. at the end of the address space (add ress 127), the counter ?rolls over? to address 0 and t he x24012 continues to output data for each acknowled ge received. refer to figure 9 for the address, acknow ledge and data transfer sequence. figure 9. sequential read figure 10. typical system configuration 3847 fhd f14 3847 fhd f15 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl v cc
x240 12 9 absolute maximum ratings* temperature under bias .................. ?65 c to +135 c storage temperature ....................... ?65 c to +150 c voltage on any pin with respect to v ss ............................... ?1.0v to +7v d.c. output current ............................... ............. 5 ma lead temperature (soldering, 10 seconds) ............................. 300 c *comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress r ating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci fication is not implied. exposure to absolute maximum rating co ndi- tions for extended periods may affect device reliab ility . recommended operating conditions temperature min. max. commercial 0 c 70 c industrial ?40 c +85 c military ?55 c +125 c 3847 pgm t02 d.c. operating characteristics (over recommended operating conditions unless other wise specified) limits symbol parameter min. max. units test conditions l cc1 power supply current (read) 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 100 khz, sda = open, all other l cc2 power supply current (write) 2 inputs = gnd or v cc ? 0.3v i sb (1) standby current 50 a scl = sda = v cc ? 0.3v, all other inputs = gnd or v cc , v cc = 5.5v i sb (2) standby current 30 a scl = sda = v cc ? 0.3v, all other inputs = gnd or v cc, v cc = 3v i li input leakage current 10 a v in = gnd to v cc i lo output leakage current 10 a v out = gnd to v cc v ll (2) input low voltage ?1.0 v cc x 0.3 v v ih (2) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3 ma 3847 pgm t04 capacitance t a = 25 c, f = 1.0mhz, v cc = 5v symbol test max. units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a 0 , a 1 , a 2 , scl, wc) 6 pf v in = 0v 3847 pgm t06 notes: (1) must perform a stop command prior to measuremen t. (2) v il min. and v ih max. are for reference only and are not tested. (3) this parameter is periodically sampled and not 100% test ed. supply voltage limits x24012 4.5v to 5.5v x24012-3 3v to 5.5v x24012-2.7 2.7v to 5.5v 3847 pgm t03
x24012 10 a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 3847 pgm t07 bus timing note: (4)t pur and t puw are the delays required from the time v cc is stable until the specified operation can be init iated. these param- eters are periodically sampled and not 100% tested. power - up timing symbol parameter max. units t pur (4) power-up to read operation 1 ms t puw (4) power-up to write operation 5 ms 3847 pgm t09 read & write cycle limits symbol parameter min. max. units f scl scl clock frequency 0 100 khz t i noise suppression time constant at scl, sda inputs 100 ns t aa scl low to sda data out valid 0.3 3.5 s t buf time the bus must be free before a new transmission can start 4.7 s t hd:sta start condition hold time 4.0 s t low clock low period 4.7 s t high clock high period 4.0 s t su:sta start condition setup time 4.7 s t hd:dat data in hold time 0 s t su:d at data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 4.7 s t dh data out hold time 300 ns 3847 pgm t08 a.c. characteristics limits (over recommended operating conditions unless other wise specified) equivalent a.c. load circuit 3847 fhd f17 3847 fhd f03 t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 5.0v 1533 100pf output
x24012 11 write cycle limits symbol parameter min. typ. (5) max. units t wr (6) write cycle time 5 10 ms 3847 pgm t10 the write cycle time is the time from a va lid stop condition of a write sequence to the end of the int ernal erase/program cycle. during the write cycle, the x2 4012 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycle timing 3847 fhd f04 guidelines for calculating typical values of bus pull-up resistors symbol table must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance outputs inputs waveform 3847 fhd f16 120 100 80 40 60 20 20 40 60 80100120 0 0 bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max =1.8k notes: (5) typical values are for t a = 25 c and nominal supply voltage (5v). (6) t wr is the minimum cycle time from the system perspecti ve when polling techniques are not used. it is the maximum time the device requires to perform the internal write operation. sda 8th bit word n ack t wr stop condition start condition x24012 address scl resistance (k )
x24012 12 notes
x24012 13 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.027 (0.683) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ? 8 x 45 8 - lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in m illimeters) packaging information 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.325 (8.25) 0.300 (7.62) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.140 (3.56) 0.130 (3.30) 0.020 (0.51) 0.015 (0.38) pin 1 seating plane 0.062 (1.57) 0.058 (1.47) 0.255 (6.47) 0.245 (6.22) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 0.092 (2.34) dia. nom. half shoulder width on all end pins optional 0.015 (0.38) max. 8 - lead plastic dual in-line package type p
x24012 14 x24012 p t g - v device ordering information v cc limits blank = 4.5v to 5.5v 3 = 3.0v to 5.5v 2.7 = 2.7v to 5.5v temperature range blank = commercial = 0 c to +70 c i = industrial = ?40 c to +85 c m = military = ?55 c to +125 c package p = 8-lead plastic dip s = 8-lead soic blank = 8-lead soic p = 8-lead plastic dip s = 8-lead soic g = rohs compliant lead free blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, ?40 c to +85 c d = 3.0v to 5.5v, 0 c to +70 c e = 3.0v to 5.5v, ?40 c to +85 c f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?40 c to +85 c limited warranty devices sold by xicor, inc. are covered by the warranty and p atent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the info rmation set forth herein or regarding the freedom of the described devices from patent infringement. xicor , inc. makes no warranty of merchantability or fitness for any purpose. x icor, inc. reserves the right to discontinue production an d change specifications and prices at any time and witho ut notice. xicor, inc. assumes no responsibility for the use of any circ uitry other than circuitry embodied in a xicor, inc. prod uct. no other circuits, patents, licenses are implied. u.s. patents xicor products are covered by one or more of the followin g u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,3 14,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,7 06; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4, 874, 967; 4,883, 976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may en danger life, system designers using this product should desi gn the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicor's products are not authorized for use in critical co mponents in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, o r (b) support or sustain life, and whose failure to perform, when properly used in accordance wit h instructions for use provided in the labeling, can be reasonably expected to result in a signif icant injury to the user. 2. a critical component is any component of a life suppor t device or system whose failure to perform can be reason ably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. x24012 x g x part mark convention g= rohs compliant lead free package blank = standard package. non lead free

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